The present invention relates to a control of a liquid crystal display, and more particular to a liquid crystal display device having a display control circuit for transferring video data to a liquid crystal display panel.
In recent years, high definition of a display image of a computer, a television, etc. has been enhanced, and in the liquid crystal display device for treating video date thereof (image data), the data bus number and the data transfer speed have been increased year by year with an increase in the pixel number and the gradation number.
FIG. 8 is a diagram illustrating a system configuration of the conventional liquid crystal display device. It is composed of an image rendering device 2A such as a personal computer (PC) and a liquid crystal display device 1A, and the liquid crystal display device 1A is configured of: a display control circuit (timing controller) 11A for inputting video data such as parallel data, synchronous data associated with the above video data, etc. from the image rendering device 2A to output the predetermined video data and control signal to an internal bus; a signal-line driving circuit (source driver) 14A for inputting a signal-side control signal that is composed of the video data from the display control circuit 11A and known synchronous signals (HCK: a timing signal for incorporating the video data, STH: a horizontal start pulse, etc.), and a reference gradation voltage from a reference gradation voltage generation circuit 12A to output the video data as a gradation voltage to a signal line; a scan-line driving circuit (gate driver) 13A for inputting a scan-side control signal of the display control circuit 11A to output a signal for selecting/scanning a scan line; and a liquid crystal display panel 15A that comprises a matrix-shape signal line and scan line and has a source/gate electrode of a TFT transistor connected to an intersection, and a drain electrode connected to a pixel electrode respectively.
In such a liquid crystal display device, the video data to be input/output into/from the display control circuit 11A in the interior of the device is transferred as parallel data via a data bus that is composed of a plurality of the signal lines; however due to upsizing of the liquid crystal display panel, an increase in the pixel number thereof, the high definition of the display image, etc. the bit number of the video data is increased, the inversion number of the bit (bit inversion number) is also increased between the previously positioned data and the subsequently positioned data in a continuous sequence of the output video data (referred to as “previous data”, and “subsequent data” respectively), and when the bit inversion number is large, radiation of a harmonic component caused by switching the data and from the bus augments, thus causing electromagnetic interference (EMI) to occur.
Thereupon, it was proposed as a method of restraining such electromagnetic radiation that the bit inversion number of the subsequent data relative to the previous data of the video data was compared in the data order, the subsequent data of which the bit inversion number became more than half of the bit number of the data was converted into the video data controlled so that the bit inversion number between two pieces of the data was constantly equal to or less than half, by performing such a data process to invert its logical level, and that simultaneously therewith, an inversion signal (POL2) indicating whether or not the logical level was inverted was added as one of the foregoing signal-side control signals to transfer both signals within the liquid crystal display device (JP-P2001-356737A).
FIG. 9 is a conceptual view illustrating a control of the bit inversion number in the data transfer between the display control circuit and the signal-line driving circuit. Also, FIG. 10 is a conceptual view illustrating an example of the data transfer. The display control circuit 11A is provided with a bit comparator 112, an inversion/noninversion circuit (1) 114, etc. In the display control circuit 11A, the input video data is input, data (previous data) 111 sent just before is compared with data (subsequent data) 113 that is to be sent from now on in the bit comparator 112, an inversion or a noninversion of the subsequent data is made in the inversion/noninversion circuit (1) 114 by whether or not the comparison result is more than half of the bit number of the above video data to output it to the data bus, and, simultaneously therewith, an inversion signal (POL2) of one signal line of the signal-side control signals is taken as the active (its logic state is an “H” level), etc.
Also, the signal-line driving circuit 14A is provided with an inversion/noninversion circuit (2) 141, and a data register 142 in which data is filed. The inversion/noninversion circuit (2) 141 takes a control of receiving the video data and the inversion signal to be input via the data bus, of inverting the video data, which was input, to output it to the data register 142 in the event that the inversion signal is at an “H” level, and of outputting the video signal, which was input, as it stands to a data register 142 in the event that the inversion signal is not at the “H” level (“L” level), based on the inversion signal data by data, and reproduces the original data to latch it to the data register 142 in preparation for conversion thereof into the gradation voltage that is to be made afterward.
FIG. 11 is a view illustrating an example of the video data obtained by taking a control of the bit inversion for the 24-bit input video data of red (R), green (G), and blue (B). 24-bit parallel data R7 (0) . . . R0 (0), G7 (0) . . . G0 (0), and B7 (0) . . . B0 (0) shown firstly is a signal of the noninversion, of which the inversion signal is at the “L” level, 24-bit parallel data R7 (1)^ . . . R0 (1)^, G7 (1)^ . . . G0 (1)^, and B7 (1)^ . . . B0 (1)^ shown secondly is a signal of the inversion (^ indicates the inversion), of which inversion signal is at the “H” level, and those that follow are the same.
Also, as a method of dealing with an increase in the bit number of the video data to curtail the data bus number, the method has been considered of serializing one part of the parallel data to curtail the bit number. Furthermore, executing a control of the bit inversion number for such video data as well can be considered.
FIG. 12 is a view illustrating a timing chart of a data form of the data bus and the inversion signal, as one example, in the event of making a serial transfer at a ratio of 2 to 1. As to the input video data of 24-bit parallel data, it has the data form of a 12-bit parallel serialized partially (2 bits) in a form that its even bit is piled on the odd bit in multiple in a time-division manner. Herein, a clock CH is a clock signal of the input video data prior to partial serialization, and a clock HCK is a clock signal of the 12-bit parallel data after partial serialization. As seen from the same figure, a data rate (data speed) of the 12-bit parallel data is two times as quick as that of the 24-bit parallel data.
As mentioned before, in the liquid crystal display device, the data bus number and the data transfer speed have been increased with an increase in the pixel number and the gradation number due to the upsizing of the display screen, the high definition of the display image, etc., whereby it is of importance to restrain the electromagnetic interference, and to curtail the data bus number. Herein, it is effective to take an inversion control of the logical level of the data in order to restrain the electromagnetic interference, and also, it is effective to partially serialize the parallel data in order to curtail the data bus number.
As it is, when the parallel data is serialized partially, as a result, the data speed of the partially serialized video data is increased by the multiple of the bit number by which the parallel data is serialized, the operational speed for the inversion control of the logical level of the data also becomes high by the same multiple, and in making a conventional inversion control of the logical level, its circuit operation is speeded up (for example, the high-speed operation is required for the bit comparator, the inversion/noninversion circuit, etc. shown in FIG. 9 to the extent that the parallel data was serialized), whereby the problem exists that a correspondence to the increase in the pixel number and the gradation number also becomes difficult. Also, the electromagnetic interference etc. caused by the switching for the inversion control of the logical level is also derived as a new problem.